Porto, Portugal · Silicon & hardware security

André Barbosa

ASIC Digital Design Engineer

I write RTL for high-speed connectivity IP at Synopsys — HDMI, DisplayPort, UFS — and I research how microarchitecture leaks the secrets it was built to protect.

Currently
Synopsys · HDMI/DisplayPort IP RTL implementation
Focus
RTL design, micro-architecture, side-channel analysis
Education
MSc Electrical & Computer Engineering, U. Minho
Download CV Email LinkedIn GitHub

Experience

  1. Dec 2024 — Present

    ASIC Digital Design Engineer

    Synopsys · HDMI/DisplayPort IP RTL implementation team

    • Design, implement and debug RTL in Verilog and SystemVerilog for high-speed connectivity IP, across micro-architecture, simulation and debug, synthesis, and lint/CDC sign-off.
    • Contributed automotive safety-related RTL to the UFS4 IP under ISO 26262 design practices, working to functional-safety requirements.
    • Work daily in production EDA flows — VCS, Verdi, Design Compiler, Fusion Compiler, SpyGlass, Formality — on Linux with Perforce and Jira.

    Earlier as a summer intern (Jul – Sep 2023): built a DisplayPort video-packetisation RTL module.

  2. Jan — Nov 2024

    Researcher

    neXt Sense · Safety of Connected and Automated Vehicles

    • Investigated side-channel attacks against automotive sensors and established realistic threat models for connected and automated vehicles.

Education

  1. 2022 — 2024

    MSc, Electrical and Computer Engineering

    University of Minho · Embedded Systems and Computers

    Thesis Multi-Run Software-Based Microarchitectural Side-Channel Attacks Against MCUs — practical software-only attacks that recover keys from cryptographic routines running on ARM Cortex-M IoT devices.

  2. 2019 — 2022

    BSc, Electrical and Computer Engineering

    University of Minho

Research & projects

Peer-reviewed · EWSN ’24

BUSted Second Stop! A First Step for Breaking Cryptographic Applications on MCU-based IoT Devices

Software-based side-channel attacks against cryptographic implementations on ARM Cortex-M IoT devices, exploiting microarchitectural leakage to recover secrets without any physical access to the target.

Read the paper

FPGA SoC · Cryptographic IP

Twofish IP core

Hardware implementation of the Twofish block cipher on an FPGA SoC, balancing throughput, area, and resilience against the cipher's known implementation weaknesses.

FPGA SoC · Verilog

8051 assisted computer system

A pipelined 8051 SoC in Verilog with a custom image-processing accelerator, alongside VGA and PS/2 controllers, brought up on FPGA.

Embedded vision

Driver Drowsiness Detection

A real-time drowsiness detector on Raspberry Pi using multi-threaded machine learning, with a companion mobile app and backing database.

Skills

Hardware design
RTL designVerilogSystemVerilogMicro-architectureASIC flowFPGA prototyping
Verification
SystemVerilog testbenchesFunctional coverageUVM
EDA tools
VCSVerdiDesign CompilerFusion CompilerSpyGlass — lint/CDCFormalityVivadoVitis
Hardware security
Side-channel analysisCryptographic IPMCU threat modellingARM Cortex-M security
Embedded
ARM Cortex-MSTM32RTOSLow-level systems programming
Software
CC++AssemblyPythonBash
Workflow
LinuxGitPerforceJira
Languages
Portuguese — nativeEnglish — fluent

Contact

Happy to talk about RTL, micro-architecture, or anything that leaks.